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Recording: Performance Engineering Techniques Behind 1BRC


This is the recording of the live session covering some of the performance engineering techniques behind problems like 1BRC. We tried to cover a lot of ground:

  • Background on X86 ISA and some assembly code patterns

  • Compiler level optimizations

  • Microarchitecture level features of X86

    • Instruction level parallelism

    • Branch prediction

    • Caches

  • Finally, we went through a 1BRC implementation. Where we went through different improved versions of the implementation, each version built on the previous one by fixing one of the performance bottlenecks identified from the flamegraph.

There was a lot more to cover with very limited time. I would have loved to spend more time on 1BRC code, or even cover some more optimization techniques.


You can access the slides here, and the 1BRC code that we discussed here.

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